1. Technical Field
The disclosure relates in general to a semiconductor element, a manufacturing method thereof and an operating method thereof, and particularly to a semiconductor element, a manufacturing method thereof and an operating method thereof used for electrostatic discharge (ESD) protection.
2. Description of the Related Art
Extended drain MOSFET (EDMOSFET), lateral double-diffused MOSFET (LDMOSFET), and reduced surface field (RESURF) technology are used as high-voltage elements for manufacturing output drivers due to the compatibility with existing CMOS processes. The electrostatic discharge (ESD) performance of typical high-voltage devices often depends on the total width and surface or lateral rules of the corresponding devices.
High-voltage devices typically have characteristics that include a low on-state resistance (Rdson), a high breakdown voltage and a low holding voltage. The low on-state resistance may tend to make an ESD current more likely to concentrate on the surface or the drain edge of a device during an ESD event. High current and high electric fields may cause the physical destruction at a surface junction region of such a device. Based on the typical requirement for a low on-state resistance, the surface or lateral rules likely cannot be increased. Thus, ESD protection may be a challenge.
The high breakdown voltage characteristic of high-voltage devices typically means that the breakdown voltage is higher than the operating voltage, and the trigger voltage (Vt1) is higher than the breakdown voltage. Accordingly, during an ESD event, the internal circuitry of the high-voltage device may be at risk of damage before the high-voltage device turns on for ESD protection. The low holding voltage characteristic of high-voltage devices also leaves open the possibility that unwanted noise associated with a power-on peak voltage or a surge voltage may be triggered or that a latch-up may occur during normal operation. High-voltage devices may also experience the field plate effect due to the fact that electric field distribution may be sensitive to routing so that ESD current may be likely to concentrate at the surface or drain edge during an ESD event.
To improve high-voltage device performance with respect to ESD events, one technique that has been implemented involves the additional use of masks and other processes to create a larger sized diode within bipolar junction transistor (BJT) components and/or increasing the surface or lateral rules for MOS transistors.
Accordingly, it may be desirable to develop an improved structure for providing ESD resistance.